ED Sciences Physiques et de l'Ingénieur
Architecture and design of integrated circuits in 22 nm CMOS technology for millimeter V-band wireless interfacing applications
by Martin VIDAL (Laboratoire de l'Intégration du Matériau au Système)
The defense will take place at 14h30 - Amphithéâtre Jean-Paul DOM UMR 5218 - IMS - Laboratoire de l'Intégration du Matériau au Système 351 Cours de la Libération, 33405 Talence Cedex, France
in front of the jury composed of
- Thierry TARIS - Professeur - Laboratoire IMS - Directeur de these
- Thierry PARRA - Professeur - LAAS-CNRS - Rapporteur
- Jean-Baptiste BEGUERET - Professeur - Laboratoire IMS - CoDirecteur de these
- Antoine FRAPPE - Professeur - IEMN - Rapporteur
- David DUBUC - Professeur - LAAS-CNRS - Examinateur
Millimeter-wave communications in the V-band (57--64~GHz) represent a promising solution for replacing high-speed wired interfaces through wireless links, thanks to their large available bandwidth and inherent spatial confinement. However, reproducing the performance of standards such as USB 3.2 (10~Gb/s, BER $leq 10^{-12}$, latency $< 3$~ns) remains a major challenge in terms of power consumption, robustness, and architectural complexity. This thesis presents the design of a CMOS millimeter-wave receiver capable of supporting a USB 3.2-class wireless link over short-range distances from 5~mm to 5~cm. A hierarchical design methodology combining top-down and bottom-up approaches is employed to translate system-level constraints into RF circuit specifications and to validate architectural choices. The main contribution of this work is the design of a 60~GHz reconfigurable low-noise amplifier incorporating a transformer-based inter-stage network and a continuous gain control mechanism over a 10--20~dB range without significant degradation of the noise figure. In addition, a stacked passive device technique is introduced, enabling a 40--55% reduction in silicon area. The receiver architecture is based on a dual-path I/Q downconversion scheme combining the proposed LNA, a splitter- and balun-based impedance matching network, and active mixers. System-level analysis and validation show a total gain of approximately 38~dB, a noise figure of 6.5~dB, and a power consumption of 52.5~mW. The overall performance achieves a BER below $10^{-12}$ with a latency below 1~ns. This work demonstrates the feasibility of a low-latency, energy-efficient analog millimeter-wave receiver, paving the way toward wireless replacement of high-speed wired interfaces.