ED Sciences Physiques et de l'Ingénieur
Architecture design methodology for spike encoding targeting biological signal processing
by Clémence GILLET (Laboratoire de l'Intégration du Matériau au Système)
The defense will take place at 9h30 - Amphi G ENSEIRB-Matmeca 1 Avenue du Dr Albert Schweitzer 33400 Talence
in front of the jury composed of
- Philippe COUSSY - Professeur des universités - Université Bretagne Sud - Rapporteur
- Benoît MIRAMOND - Professeur des universités - Université Côte d'Azur - Rapporteur
- Sylvie RENAUD - Professeure des universités - Bordeaux INP - Examinateur
- Cristell MANEUX - Professeure des universités - Université de Bordeaux - Examinateur
Artificial Intelligence (AI) has revolutionized many fields such as health, industry, automobiles and home automation. AI algorithms include artificial neural networks, the complexity of which has continued to increase in recent years. This development has made it possible to achieve pattern recognition performance close to human performance, in particular thanks to Deep Learning. However, these results are obtained at the expense of significant energy costs, hindering the deployment of these algorithms on systems with strong constraints such as embedded systems. To overcome these limitations, models of artificial neural networks inspired by biology tend to emerge, and in particular spiking neural networks. Integrated into dedicated hardware accelerators, the use of these networks makes it possible to significantly reduce energy consumption as well as processing time within embedded systems. However, due to the lack of event-driven sensors that can be directly interfaced with spiking neural networks, the real-world use cases for these systems are limited. In addition, the scarcity of existing event-based sensors leads developers to use conventional sensors and to add an encoding layer in order to produce spikes that can be used by spiking neural networks. The reduced number of hardware implementations integrating such encoding systems, associated with the difficulty of transposition to different applications, limits the development of hardware architectures of spiking neural networks. We therefore propose a methodology to generate, optimize and evaluate digital spike encoding architectures. The tools developed make it possible to integrate a wide range of encoding algorithms and adapt them to numerous data types. Thanks to its versatility, the methodology allows the user to quickly generate a high number of architectures meeting different compromises depending on application constraints. The first step of the framework relies on automation scripts that generate adapted behavioral models described in C/C++. These models are then transmitted to a tool based on high level synthesis and making it possible to produce a panel of architectures for each of the previously generated models. Finally, a real condition testing environment was developed in order to evaluate the performances of the different solutions produced and to select the better regarding the application constraints. For demonstration purposes, we applied this methodology to a low-cost and compact FPGA. Two encoding algorithms presenting different approaches have been integrated. The first algorithm integrates frequency pre-processing to separate the signal into different components, before encoding the latter in the form of spikes using bio-inspired neurons. The second algorithm is based on the use of sensory neurons which have the advantage of not requiring pre-processing and producing a temporal representation of the signal. Using the methodology, it was possible to generate several dozen architectures presenting varied temporal and energy performances in a very short time. Using the results from the comparison of architectures makes it possible to select the optimal solution according to the application constraints. The methodology that we have developed can virtually integrate any encoding algorithm and could be extended to the generation and optimization of digital architectures of spiking neural networks in order to facilitate and accelerate their deployment.