ED Sciences Physiques et de l'Ingénieur
Characterization and modelling of vertical junctionless silicon nanowire field-effect transistors for 3D logic circuits
by Yifan WANG (Laboratoire de l'Intégration du Matériau au Système)
The defense will take place at 9h30 - Amphithéatre J P DOM Laboratoire IMS CNRS UMR 5218 351 Cours de la Libération, Bâtiment A31 33405 Talence Cedex, France
in front of the jury composed of
- Chhandak MUKHERJEE - Chargé de recherche - Université de Bordeaux - Directeur de these
- Elena GNANI - Professeure des universités - Università di Bologna - Rapporteur
- Benjamin INIGUEZ NICOLAU - Professeur des universités - University Rovira i Virgili - Rapporteur
- Guilhem LARRIEU - Directeur de recherche - LAAS-CNRS, Université de Toulouse, CNRS - Examinateur
- Marina DENG - Maîtresse de conférences - Université de Bordeaux - CoDirecteur de these
- François MARC - Maître de conférences - Université de Bordeaux - Examinateur
To respond to today's growing demand for computing hardware, neuromorphic architectures have emerged as a potential hardware solution to circumvent the von Neumann bottlenecks by minimizing the transmission delay between computing and storage units. To address this trend, LAAS laboratory has developed an emerging 18nm Junction-less Vertical Silicon Nanowire Transistor (JL-VNWFET) technology, promising low-latency, low-energy, high-density performances for in-memory computing applications. The junctionless (JL) structure formed through high doping of vertical silicon nanowires not only simplifies the fabrication process, its gate-all-around (GAA) structure also offers robustness to the short channel effects (SCE). The inherent 3D vertical structure allows for the stacking of multiple gates to increase the number of transistors per unit area. However, due to aggressive scaling, electrothermal and trapping effects have become critical concerns that can impact the electrical characteristics of the transistors, thus resulting in dominant reliability issues. In order to investigate the potential of this emerging technology for circuit applications, physics-based compact models are therefore a prerequisite. In this thesis, we present extensive static and dynamic characterization of this technology including thermal and reliability measurements, associated compact model development and analysis of underlying degradation mechanisms. First, the compact model and its scalability are validated against extensive static characterization. To analyse the electro-thermal effects, we then performed DC and pulse measurements at different temperatures. The results were then analysed to extract the thermal impedance, describing the device dynamic self-heating, and trap information that are then integrated into the existing compact model. We then performed logic circuit simulations using the improved compact model, which demonstrated that self-heating and trapping effects could significantly impact the circuit figures of merit such as delay and power consumption. Subsequently, we performed accelerated aging tests on the JL-VNWFETs. To dissociate purely thermal and purely bias-induced effects, we performed temperature storage tests as well as Negative Bias Temperature Instability (NBTI) stress tests. Both measurement results showed a gradual degradation of the device threshold voltage with stress bias and time, attributed to a combination of Si-SiO2 interface trap creation and trapping in pre-existing defects. Finally, the compact model has been modified to incorporate NBTI effects. The final compact model is then used for performance prediction of logic circuits under different operating conditions. The compact model developed in this work can provide feedback to process engineers through a Design Technology Co-Optimization (DTCO) loop and remains a critical link in the value chain of 3D JL-VNWFET based hardware design.