ED Sciences Physiques et de l'Ingénieur
Fabrication, Characterization and Modelling of Emerging Field-effect Transistors
by Bruno NECKEL WESLING (Laboratoire de l'Intégration du Matériau au Système)
The defense will take place at 9h30 - Amphitheater JP. DOM Laboratoire IMS 351 Cours de la Libération, Bâtiment A31 33405 Talence Cedex, France
in front of the jury composed of
- Marina DENG - Maîtresse de conférences - Université de Bordeaux - Directeur de these
- Walter MICHAEL WEBER - Professeur des universités - Technische Universität Wien - Rapporteur
- Jean-Pierre RASKIN - Professeur des universités - Université catholique de Louvain - Rapporteur
- Guilhem LARRIEU - Directeur de recherche - LAAS-CNRS - Examinateur
- Cristell MANEUX - Professeure des universités - Université de Bordeaux - Examinateur
- Talha CHOHAN - Ingénieur de recherche - Global Foundries Fab1 - Examinateur
- Jens TROMMER - Chargé de recherche - NaMLab gGmbH - Examinateur
- Chhandak MUKHERJEE - Chargé de recherche - Université de Bordeaux - CoDirecteur de these
Scaling has been used as the way to achieve the goals of improving field-effect transistors (FETs) technology in the past several decades, making it more powerful and efficient. The scaling tends to end due to physical limits and it drives the new approaches to increase transistor and circuit functionalities. Juctionless vertical nanowire field effect transistors (JL-VNWFETs) are suited for 3D integration due to uniformly doped channels that eliminate complex doping and can be combined with a gate last process. Reconfigurable field effect transistors (RFETs) allow the properties of N- and P-Type to be combined in a single device using a multi-gate topology. The emerging technologies mentioned come with the challenge of parasitic characterization. This work aims at the challenge of fabrication and characterization of nanoscale emerging devices, focusing on the use of S-parameters measurement for the extraction of devices parameters and the use of electromagnetic simulation as a predictive tool to enhance the next fabricated devices. An equivalent circuit for the access parasitics of the JL-VNWFETs was proposed with the objective of improving the de-embedding results. The changes in the layout for the measurement structure of the JL-VNWFETs provided a decrease in total pad capacitance. For industrial fabricated back bias RFETs, high frequency characteristics were extracted for the first time, and a small signal equivalent circuit was proposed. For laboratory-made dual-gated RFETs, a layout of measurement structures is proposed, and the effect of the silicon on the insulator (SOI) substrate was studied along the extraction of parameters from DC and S-parameters measurements.