ED Sciences Physiques et de l'Ingénieur
Technology optimization of a vertical SiGe HBT on bulk substrate and Evaluation of a new SiGe HBT architecture on FD-SOI
by Philippine BILLY (Laboratoire de l'Intégration du Matériau au Système)
The defense will take place at 10h30 - Amphi J.P. Dom UMDR 5218, IMS, Laboratoire de l'Intégration du Matériau au Système, 351 Cours de la Libération, 33405 Talence Cedex (France)
in front of the jury composed of
- Sébastien FREGONESE - Chargé de recherche - Université de Bordeaux - Directeur de these
- Nathalie DELTIMPLE - Professeure - Université de Bordeaux - Examinateur
- Fabien PASCAL - Professeur des universités - Université de Montpellier - Rapporteur
- Philippe FERRARI - Professeur - Université Grenoble Alpes - Rapporteur
- Bertrand ARDOUIN - Docteur - Nokia Bell Labs - Examinateur
- Thomas ZIMMER - Professeur - Université de Bordeaux - CoDirecteur de these
Silicon-Germanium (SiGe) BiCMOS technologies currently in production address applications such as 77 GHz automotive anti-collision radar and 100 Gb/s optical communications for the Internet. The next generations of BiCMOS technology will improve these applications and pave the way for new applications, including 400 Gb/s optical communications, ultra-high-speed wireless communications, and the development of sensors and imagers for medical, security, and space domains. The work presented in this thesis focuses on the development and optimisation of silicon-germanium hererojonction bipolar transistor (SiGe HBT) on bulk and FD-SOI substrates. For the bulk substrate, the reference technology used is STMicroelectronics' BiCMOS055X, offering a fT of 380 GHz and a fMAX of 500 GHz. For the FD-SOI substrate, the research was conducted on an advanced CMOS technology. Initially, the research focused on optimizing the BiCMOS055X technology. The first improvement axis concerns the frequency characterization method for bipolar transistors, implementing a 16-term error calibration (16T) combined with an advanced de-embedding process. This calibration enables reliable measurements up to 500 GHz, allowing for the precise extraction of the authentic fMAX and the observation of second-order effects, such as the impact of the substrate network. The second optimization axis focuses on the transistor structure, including morphological modifications and doping profile adjustments. Regarding morphology, adjustments were made to the substrate network: optimizing the layout of the collector-substrate region improved the fMAX by 10% at frequencies above 100 GHz. Concerning the doping profile, part of the work is dedicated to optimizing the profile of the intrinsic base. This includes the development and calibration of the in-situ epitaxy recipe for the boron-doped SiGeC:B layer, to better control key parameters of the layer, such as its thickness and boron dose. Subsequently, the research shifted toward evaluating a lateral HBT architecture integrated into an FD-SOI CMOS technology. This section presents the integration of a new HBT architecture in this type of technology, along with the associated integration constraints. Two architectures compatible with the studied process flow were integrated on silicon and characterized. The results highlight the challenges of integrating a lateral HBT into an unmodifiable CMOS process. Finally, a TCAD study proposes additions and modifications to certain process steps to facilitate the integration of a lateral HBT.