ED Droit
The evolutionary integration of health and environmental considerations into trade agreements
by Carla GOMEZ (CENTRE DE RECHERCHES ET DE DOCUMENTATION EUROPÉENNES ET INTERNATIONALES)
The defense will take place at 14h00 - Salle des thèses Salle des thèses, Rdc, Bat C, Avenue Léon Duguit, 33600 Pessac
in front of the jury composed of
- Baptiste TRANCHANT - Professeur des universités - Université de Bordeaux - Directeur de these
- Richard OUELLET - Professeur - Université Laval - CoDirecteur de these
- Gabrielle MARCEAU - Professeure - Université Laval - Examinateur
- Hugues HELLIO - Professeur des universités - Université d'Artois - Rapporteur
- Sophie GROSBON - Professeure des universités - CEDIN - Université Paris Nanterre - Rapporteur
- Sabrina ROBERT - Professeure des universités - Nantes Université - Examinateur
Integrating health and environmental considerations into trade agreements has long been a subject of debate, and questions remain as to how these issues are and should be articulated. This thesis shows that the way in which trade agreements aimed at liberalizing trade in goods take account of these issues is plural and rapidly evolving – or even mutating. The aim of this work is to propose a systemic and comprehensive analysis of the tools used to integrate these considerations into trade agreements since the advent of the World Trade Organization. This will enable us to propose a general categorization of these tools, while assessing their conciliatory potential. Drawing lessons from the shortcomings and limitations of each tool, it will also suggest avenues for improvement. In doing so, it will enable a comprehensive and up-to-date analysis of the means at our disposal to reconcile trade with health and environmental issues. It also demonstrates the transformative evolution for free trade of the reconciliation between commercial imperatives and health and environmental considerations.
ED Sciences Physiques et de l'Ingénieur
Study and implementation on ASIC of low cost RISC-V instruction set architectures
by Filipe POUGET (Laboratoire de l'Intégration du Matériau au Système)
The defense will take place at 14h15 - Laboratoire IMS, Amphitéâtre J.P.DOM 351 Cours de la Libération, Bâtiment A31, 33405 Talence Cedex, France
in front of the jury composed of
- Christophe JEGO - Professeur des universités - Université de Bordeaux - Directeur de these
- Camille LEROUX - Maître de conférences - Université de Bordeaux - CoDirecteur de these
- Sylvain CLERC - Ingénieur de recherche - CEA LIST - Examinateur
- Andrea PINNA - Professeur des universités - Sorbonne Université - Examinateur
- Matthieu ARZEL - Professeur - IMT Atlantique - Rapporteur
- David NOVO - Directeur de recherche - LIRMM - Rapporteur
In the design of microcontrollers, performance, power consumption, energy consumption, and silicon area are key metrics that must be carefully balanced. Performance typically refers to how quickly the microcontroller can execute a task, power consumption is the rate at which the device uses electrical power during operation, energy consumption defines the autonomy, and finally, area refers to the amount of silicon space required to implement the microcontroller on a chip. These four factors are tightly linked with each other, leading to choices made by designers to achieve an optimal balance for the intended application. In this context, the open-source RISC-V Instruction Set Architecture (ISA) has recently gained widespread adoption, enabling the creation of a diverse range of CPU cores. Its modular and extensible design allows the ISA to be customized for different application domains, from energy- efficient embedded systems to high-performance computing platforms. Within this framework, the IMS laboratory developed AsteRISC, a configurable non-pipelined RISC-V processor core designed to efficiently support Design Space Exploration (DSE). The architecture is based on a flexible control unit that can adapt to different architectural parameters. The research initially focuses on analyzing the energy consumption of AsteRISC implemented in STMicroelectronics 18nm FD-SOI CMOS technology. After porting AsteRISC to this technology and evaluating its performance, several approaches to improve its energy efficiency are explored. The study assesses the impact of integrating extensions from the RISC-V standard, along with architectural and implementation-level optimizations. Finally, the influence of the implementation frequency on overall energy consumption is investigated. Three custom RISC-V instructions are then proposed and implemented in the AsteRISC CPU core. The instructions lwincr and swincr, which extend the standard load and store operations, and convcat, which accelerates the execution of a specific sequence of conversion operations, are introduced. These custom instructions contribute to reducing the overall energy consumption of AsteRISC. Finally, the CPU core is integrated into a System-on-Chip (SoC) that couples AsteRISC with a hardware accelerator dedicated to Large Language Model (LLM) workloads. Within this SoC, AsteRISC handles control operations, data transfers, and non-linear computations. Several architectural modifications are introduced to optimize latency, power consumption, and overall energy efficiency. The SoC was subsequently fabricated, and silicon measurements were performed to evaluate its performance.